Design Trade‐Offs for FPGA Implementation of LDPC Decoders

Low density parity check (LDPC) decoders represent important throughput bottlenecks, as well as major cost and power-consuming components in today\u27s digital circuits for wireless communication and storage. They present a wide range of architectural choices, with different throughput, cost, and error correction capability trade-offs. In this book chapter, we will present an overview of the main design options in the architecture and implementation of these circuits on field programmable gate array (FPGA) devices. We will present the mapping of the main units within the LDPC decoders on the specific embedded components of FPGA device. We will review architectural trade-offs for both flooded and layered scheduling strategies in their FPGA implementation

A Log-Likelihood Ratio based Generalized Belief Propagation

In this paper, we propose a reduced complexity Generalized Belief Propagation (GBP) that propagates messages in Log-Likelihood Ratio (LLR) domain. The key novelties of the proposed LLR-GBP are: (i) reduced fixed point precision for messages instead of computational complex floating point format, (ii) operations performed in logarithm domain, thus eliminating the need for multiplications and divisions, (iii) usage of message ratios that leads to simple hard decision mechanisms. We demonstrated the validity of LLR-GBP on reconstruction of images passed through binary-input two-dimensional Gaussian channels with memory and affected by additive white Gaussian noise.This item from the UA Faculty Publications collection is made available by the University of Arizona with support from the University of Arizona Libraries. If you have questions, please contact us at [email protected]

Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation

International audienceThis paper proposes a holistic approach that addresses both the message mapping in memory banks and the pipeline-related data hazards in low-density parity-check (LDPC) decoders. We consider a layered hardware architecture using single read/single write port memory banks. The throughput of such an architecture is limited by memory access conflicts, due to improper message mapping in the memory banks, and by pipeline data hazards, due to delayed update effect. We solve these issues hy 1) a residue-based layered scheduling that reduces the pipeline related hazards and 2) off-line algorithms for optimizing the message mapping in memory banks and the message read access scheduling. Our estimates for different LDPC codes indicate that the hardware usage efficiency of our layered decoder is improved by 3%-49% when only the off-line algorithms are employed and by 16%-57% when both the residue-based layered architecture and the off-line algorithms are used

Analysis and implementation of on-the-fly stopping criteria for layered QC LDPC decoders

International audienc